1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming source/drain regions that are positioned at least partially inside a generally U-shaped semiconductor material by using a plurality of placeholder source/drain structures and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, horizontal and vertical nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region. The gate structures for such transistor devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded. In contrast to a planar transistor device, which as the name implies has a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. That is, the gate structure of a FinFET device may be positioned around both the sides and the upper surface of a portion of a fin that was previously defined in the substrate to thereby form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. That is, unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. For a given foot-print, FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices.
Another known transistor device is typically referred to as a nanowire device or sometimes a “gate all around” device. In a nanowire device, at least the channel region of the device is comprised of one or more very small diameter, wire-like semiconductor structures. As with the other types of transistor devices discussed above, current flow through a nanowire device is controlled by setting the voltage applied to the gate electrode. When an appropriate voltage is applied to the gate electrode, the channel region of the nanowire device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region, i.e., current flows through the nanowire structure.
As device dimensions have decreased, it is becoming ever more challenging to maintain adequate control of the channel region of transistor devices during operation. Device designers have used various techniques to insure that there is adequate capacitive coupling between the gate electrode of the device and the channel region of the device during operation. Absent proper capacitive coupling, control of the channel region is difficult and may result in devices having less desirable electrical performance capabilities.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further gate length reduction below 15 nm is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors). Device designers are also under constant pressure to reduce the physical size of integrated circuit products, especially products intended for mobile applications such as laptop computers, cell phones, etc. Thus, increasing the packing density of transistor devices in such integrated circuit products is always a desirable goal.
The present disclosure is directed to various semiconductor devices with a gate positioned at least partially inside a generally U-shaped channel semiconductor material by using a plurality of placeholder source/drain structures and various methods of making such devices that may reduce or eliminate one or more of the problems identified above.